counter_tb.v Source

1	// SPDX-License-Identifier: MIT
2	// Testbench for counter.v. This file is for simulation, not synthesis.
3	`timescale 1ns/1ps
4
5	module counter_tb;
6	reg clk = 1'b0;
7	reg rst = 1'b1;
8	reg en = 1'b0;
9	wire [7:0] count;
10
11	counter #(.WIDTH(8)) dut (
12	.clk(clk),
13	.rst(rst),
14	.en(en),
15	.count(count)
16	);
17
18	always #5 clk = ~clk;
19
20	initial begin
21	$dumpfile("counter_tb.vcd");
22	$dumpvars(0, counter_tb);
23
24	#12 rst = 1'b0;
25	#10 en = 1'b1;
26	#80 en = 1'b0;
27	#20 en = 1'b1;
28	#40 $finish;
29	end
30
31	initial begin
32	$monitor("time=%0t rst=%b en=%b count=%0d",
33	$time, rst, en, count);
34	end
35	endmodule