// SPDX-License-Identifier: MIT
// Testbench for counter.v. This file is for simulation, not synthesis.
`timescale 1ns/1ps

module counter_tb;
    reg clk = 1'b0;
    reg rst = 1'b1;
    reg en = 1'b0;
    wire [7:0] count;

    counter #(.WIDTH(8)) dut (
        .clk(clk),
        .rst(rst),
        .en(en),
        .count(count)
    );

    always #5 clk = ~clk;

    initial begin
        $dumpfile("counter_tb.vcd");
        $dumpvars(0, counter_tb);

        #12 rst = 1'b0;
        #10 en = 1'b1;
        #80 en = 1'b0;
        #20 en = 1'b1;
        #40 $finish;
    end

    initial begin
        $monitor("time=%0t rst=%b en=%b count=%0d",
                 $time, rst, en, count);
    end
endmodule