Makefile Source

1	SIM ?= iverilog
2	RUN ?= vvp
3	YOSYS ?= yosys
4
5	.PHONY: all sim synth clean
6
7	all: hello sim
8
9	hello: hello_world.vvp
10	$(RUN) hello_world.vvp
11
12	hello_world.vvp: hello_world.v
13	$(SIM) -g2012 -Wall -o $@ hello_world.v
14
15	sim: counter_tb.vvp
16	$(RUN) counter_tb.vvp
17
18	counter_tb.vvp: counter.v counter_tb.v
19	$(SIM) -g2012 -Wall -o $@ counter_tb.v counter.v
20
21	synth:
22	$(YOSYS) -p "read_verilog counter.v mux2.v and_gate.v traffic_light_fsm.v; synth -top counter; stat"
23
24	clean:
25	rm -f hello_world.vvp counter_tb.vvp counter_tb.vcd