SIM ?= iverilog
RUN ?= vvp
YOSYS ?= yosys

.PHONY: all sim synth clean

all: hello sim

hello: hello_world.vvp
	$(RUN) hello_world.vvp

hello_world.vvp: hello_world.v
	$(SIM) -g2012 -Wall -o $@ hello_world.v

sim: counter_tb.vvp
	$(RUN) counter_tb.vvp

counter_tb.vvp: counter.v counter_tb.v
	$(SIM) -g2012 -Wall -o $@ counter_tb.v counter.v

synth:
	$(YOSYS) -p "read_verilog counter.v mux2.v and_gate.v traffic_light_fsm.v; synth -top counter; stat"

clean:
	rm -f hello_world.vvp counter_tb.vvp counter_tb.vcd